Hex D-type Flip-Flops (with Clear)

Description This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

文件：100.31 Kbytes 页数：8 Pages

RENESAS

瑞萨

Hex D-type Flip-Flops (with Clear)

文件：121.27 Kbytes 页数：10 Pages

RENESAS

瑞萨

General-Purpose Logics-HD/RD74HC Series

Renesas

瑞萨

Hex D-type Flip-Flops (with Clear)

Description This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low sta

文件：100.31 Kbytes 页数：8 Pages

RENESAS

瑞萨

Hex D-type Flip-Flops (with Clear)

文件：121.27 Kbytes 页数：10 Pages

RENESAS

瑞萨

Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS

文件：51.75 Kbytes 页数：6 Pages

INTEGRAL

Integral Corp.