Parallel-load 8-bit Shift Register

This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.

文件：47.5 Kbytes 页数：9 Pages

HitachiHitachi Semiconductor

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Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

文件：94.65 Kbytes 页数：8 Pages

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Parallel-load 8-bit Shift Register

Description\nThis 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. •  High Speed Operation: tpd(Clock to QH) = 21 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C);

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Parallel-load 8-bit Shift Register

This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.

HITACHI

日立

Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

文件：94.65 Kbytes 页数：8 Pages

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Parallel-load 8-bit Shift Register

Description This 8-bit serial shift register shifts data from QAto QHwhen clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit. Features • High Speed Operation: tpd

文件：94.65 Kbytes 页数：8 Pages

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Parallel-load 8-bit Shift Register

文件：115.19 Kbytes 页数：10 Pages

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Parallel-load 8-bit Shift Register

文件：115.19 Kbytes 页数：10 Pages

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Parallel-load 8-bit Shift Register

文件：115.19 Kbytes 页数：10 Pages

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General-Purpose Logics-HD/RD74HC Series

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