3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

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HitachiHitachi Semiconductor

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3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

文件：229.54 Kbytes 页数：8 Pages

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3.3-V Phase-lock Loop Clock Driver

Description The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronou

文件：229.54 Kbytes 页数：8 Pages

RENESAS

瑞萨

3.3-V Phase-lock Loop Clock Driver

Description\nThe HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous • Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”\n• Phase-lock loop clock distribution for synchronous DRAM applications\n• External feedback (FBIN) pin is used to synchronize the outputs to the clock input\n• No external RC network required\n• Support spread spectrum clock (SSC);

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3.3-V Phase-lock Loop Clock Driver

HITACHI

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