140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver

Features • Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1” • Phase-lock loop clock distribution for synchronous DRAM applications • External feedback (FBIN) pin is used to synchronize the outputs to the clock input • No external RC network required • Support spread

文件：251.57 Kbytes 页数：10 Pages

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140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver

Features • Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1” • Phase-lock loop clock distribution for synchronous DRAM applications • External feedback (FBIN) pin is used to synchronize the outputs to the clock input • No external RC network required • Support spread

文件：251.57 Kbytes 页数：10 Pages

RENESAS

瑞萨

140 MHz, 0 to 85째C Operation 3.3-V Phase-lock Loop Clock Driver

Description The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchrono

文件：43.41 Kbytes 页数：11 Pages

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