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型号	下载订购	功能描述	制造商上传企业	LOGO
HD74AC74	文件：61.42 Kbytes Page：10 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：61.42 Kbytes 页数：10 Pages	HITACHIHitachi Semiconductor 日立日立公司	HITACHI
HD74AC74	文件：121.33 Kbytes Page：8 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：121.33 Kbytes 页数：8 Pages	RENESAS 瑞萨	RENESAS
HD74AC74	文件：300 bytes Page：1 Pages	Standard IC>General-Purpose Logics>HD74AC Series	Renesas 瑞萨	Renesas
HD74AC74FPEL	文件：121.33 Kbytes Page：8 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：121.33 Kbytes 页数：8 Pages	RENESAS 瑞萨	RENESAS
HD74AC74P	文件：121.33 Kbytes Page：8 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：121.33 Kbytes 页数：8 Pages	RENESAS 瑞萨	RENESAS
HD74AC74RPEL	文件：121.33 Kbytes Page：8 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：121.33 Kbytes 页数：8 Pages	RENESAS 瑞萨	RENESAS
HD74AC74TELL	文件：121.33 Kbytes Page：8 Pages	Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not dir 文件：121.33 Kbytes 页数：8 Pages	RENESAS 瑞萨	RENESAS
HD74AC74FP	文件：300 bytes Page：1 Pages	General-Purpose Logics-HD74AC Series	Renesas 瑞萨	Renesas
HD74AC74T	文件：300 bytes Page：1 Pages	General-Purpose Logics-HD74AC Series	Renesas 瑞萨	Renesas

技术参数

Family.：
HD74AC Series
Function Gr1：
Latch/Flip-Flop/Register
Function Gr2：
D type FlipFlop
Function：
Dual D-type Flip-Flops with Preset and Clear
Number of Channel：
2
Topa[Tjopa] (degC) min.：
-40
Topa[Tjopa] (degC) max.：
85
Vcc (V) min.：
2
Vcc (V) max.：
6.0
Iout (mA)：
±24
Propagation Delay (ns) max.：
10.5
Package Type：
SOP
Production Status：
Non-promotion

供应商	型号	品牌	批号	封装	库存	备注	价格
深圳市能元时代电子有限公司	HD74AC74	HIT/SOP5.2	23+		52397	##公司主营品牌长期供应100%原装现货可含税提供技术	询价
深圳市福田区绿盛电子商行	HD74AC74FPEL	HIT	2015+	SOP14	19889	一级代理原装现货,特价热卖!	询价
深圳市毅创腾电子科技有限公司	HD74AC74FPEL	HIT	23+	SOP	7000	绝对全新原装!100%保质量特价!请放心订购!	询价
深圳市一线半导体有限公司	HD74AC74FPEL	HIT	24+	SOP	2000		询价
上海鑫科润电子科技有限公司	HD74AC74FP	HIT	04+	SOP-14	4	原装现货海量库存欢迎咨询	询价
深圳市壹芯创科技有限公司	HD74AC74FPEL	HIT	22+	SOP	1148	全新原装现货!自家库存!	询价
深圳市佳鑫美电子科技有限公司	HD74AC74FP	HIT	25+	SOP	2987	只售原装自家现货!诚信经营!欢迎来电!	询价
深圳市华睿芯科技有限公司	HD74AC74FP	HIT	24+	SOP14	20000	全新原厂原装，进口正品现货，正规渠道可含税！！	询价
深圳市英卓尔科技有限公司	HD74AC74FPEL	HITACHI	20+	SOP-14	2960	诚信交易大量库存现货	询价
深圳市拓亿芯电子有限公司	HD74AC74FP	RENESAS/瑞萨	25+	SOP14	9800	全新原装现货,假一赔十	询价

更多HD74AC74供应商更新时间2026-1-28 14:08:00

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