128Mb (2Mx4Banks×16) DDR2 SDRAM

The H2A31281656B is a 128M bits DDR2 SDRAM, organized as 2,097,152words x 4 banks x 16 bits. The -25 grade parts are compliant to the DDR2 800 (6-6-6) specification . The -3 grade parts is compliant to the DDR2-667 (5-5-5) specification.\nJEDEC specifications require the refresh rate to double when \n• Power Supply: VDD, VDDQ = 1.8 V ± 0.1V \n• Double Data Rate architecture: two data transfers per clock cycle \n• Burst Length: 4 and 8 \n• Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data \n• Edge-aligned with Read data and center-aligned with Write d;

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