128Mb (2M×4Bank×16) Synchronous DRAM

The H2A11281636B is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Mega words x 4 banks by 16 bits. All inputs and outputs are synchronized with the positive edge of the clock.\nThe 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is \n• Fully Synchronous to Positive Clock Edge\n• Single 3.3V ±0.3V Power Supply\n• LVTTL Compatible with Multiplexed Address\n• Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page\n• Programmable CAS Latency (C/L) - 2 or 3\n• Data Mask (DQM) for Read / Write Masking\n• Programmable Wrap Sequenc;

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