288Mb/144Mb/72Mb Burst of 4 SigmaQuad-IITM

Features • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate in

文件：2.0357 Mbytes 页数：43 Pages

GSI

288Mb/144Mb/72Mb Burst of 4 SigmaQuad-IITM

Features • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate in

文件：2.03569 Mbytes 页数：43 Pages

GSI

288Mb/144Mb/72Mb Burst of 4 SigmaQuad-IITM

Features • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate in

文件：2.0357 Mbytes 页数：43 Pages

GSI

288Mb/144Mb/72Mb Burst of 4 SigmaQuad-IITM

Features • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate in

文件：2.0357 Mbytes 页数：43 Pages

GSI

288Mb/144Mb/72Mb Burst of 4 SigmaQuad-IITM

Features • Aerospace-Level Product • 2.0 clock Latency with DLL on • 1.0 clock Latency with DLL off • Optional DLL-controlled output timing • Can be operated with DLL on or off • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate in

文件：2.03569 Mbytes 页数：43 Pages

GSI

QUAD SRAMs

• Simultaneous Read and Write SigmaQuad Interface \n• Dual Double Data Rate Interface\n• Pipelined Read operation \n• Fully coherent Read and Write pipelines\n• ZQ mode pin for programmable output drive strength\n• IEEE 1149.1 JTAG-compliant Boundary Scan \n• JEDEC-standard pinout and package \n• Ro;

GSI

QUAD SRAMs

• Simultaneous Read and Write SigmaQuad Interface \n• Dual Double Data Rate Interface\n• Pipelined Read operation \n• Fully coherent Read and Write pipelines\n• ZQ mode pin for programmable output drive strength\n• IEEE 1149.1 JTAG-compliant Boundary Scan \n• JEDEC-standard pinout and package \n• Ro;

GSI

QUAD SRAMs

• Simultaneous Read and Write SigmaQuad Interface \n• Dual Double Data Rate Interface\n• Pipelined Read operation \n• Fully coherent Read and Write pipelines\n• ZQ mode pin for programmable output drive strength\n• IEEE 1149.1 JTAG-compliant Boundary Scan \n• JEDEC-standard pinout and package \n• Ro;

GSI