NBT SRAMs

• NBT functionality allows zero wait read-write-read bus utilization\n• LBO pin for Linear or Interleaved Burst mode\n• Internal self-timed write cycle\n• JEDEC-standard pinout and package\n• RoHS-compliant package available;

GSI

NBT SRAMs

• NBT functionality allows zero wait read-write-read bus utilization\n• Fully pin-compatible NtRAM™, NoBL™, and ZBT™ SRAMs\n• LBO pin for Linear or Interleaved Burst mode\n• Byte Write (BW) and/or Global Write (GW) operation\n• Internal self-timed write cycle\n• Automatic power-down for portable app;

GSI

SOIC-8

Gainsil(聚洵)

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SOP-8

Gainsil(聚洵)

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BGA

GSI

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