GS8342TT07BGD-300

DDR SRAMs

• SigmaDDR Interface\n• Dual Double Data Rate Interface\n• Pipelined Read operation \n• Fully coherent Read and Write pipelines\n• ZQ mode pin for programmable output drive strength\n• IEEE 1149.1 JTAG-compliant Boundary Scan\n• JEDEC-standard pinout and package\n• RoHS-compliant package available \;

GS8342TT07BGD-300

36Mb SigmaDDR-IITM Burst of 2 SRAM

GS8342TT07BGD-300I

36Mb SigmaDDR-IITM Burst of 2 SRAM

GS8552-SR

Gainsil(聚洵)
SOIC-8

Gainsil(聚洵)

GS8722-SR

Gainsil(聚洵)
SOP-8

Gainsil(聚洵)