18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

18Mb 誇1x1Dp CMOS I/O Double Late Write SigmaRAM

SigmaRAM Family Overview GS8170DW36/72A SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high pe

文件：1.00405 Mbytes 页数：32 Pages

GSI

SPECIALTY SRAMs

• Pipelined Read operation\n• Fully coherent Read and Write pipelines\n• ZQ mode pin for programmable output drive strength\n• IEEE 1149.1 JTAG-compliant Boundary Scan\n• JEDEC-standard pinout and package\n• RoHS-compliant package available;

GSI