High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

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Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

文件：718.73 Kbytes 页数：23 Pages

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GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

文件：718.73 Kbytes 页数：23 Pages

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All Devices Discontinued

文件：718.73 Kbytes 页数：23 Pages

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莱迪思

All Devices Discontinued

文件：718.73 Kbytes 页数：23 Pages

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IC CPLD 10MC 10NS 24DIP

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Package：24-DIP（0.300"，7.62mm）；包装：散装 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 10MC 10NS 24DIP

Lattice Semiconductor Corporation