Description

The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (

Features

• HIGH PERFORMANCE E2CMOS®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

— 5.5 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS® Advanced CMOS Technology

• LOW POWER CMOS

— 75 mA Typical Icc

• ACTIVE PULL-UPS ON ALL PINS

• E2CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100 Tested/100 Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS

— Uses Standard 22V10 Macrocell Architecture

— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100 Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL18V10B-15LJ属于集成电路（IC） > CPLD（复杂可编程逻辑器件）。莱迪思半导体制造生产的GAL18V10B-15LJCPLD（复杂可编程逻辑器件）CPLD 是用于执行逻辑运算和信息处理的用户可配置集成电路产品；与 PLD 或 PAL 器件相比，这些器件具有更高级别的功能（即更多的逻辑门），但低于 FPGA。CPLD 通常包含非易失性配置存储器，支持直接在器件上存储和保留用户所需的配置，并在器件断电时仍可保留这些信息。