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GAL18V10-20LP中文资料PDF规格书
GAL18V10-20LP规格书详情
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (
Features
• HIGH PERFORMANCE E2CMOS®TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
• LOW POWER CMOS
— 75 mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E2CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100 Tested/100 Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100 Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
产品属性
- 型号:
GAL18V10-20LP
- 制造商:
LATTICE
- 制造商全称:
Lattice Semiconductor
- 功能描述:
High Performance E2CMOS PLD Generic Array Logic
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
1802+ |
DIP20 |
6528 |
只做原装正品现货,或订货假一赔十! |
询价 | ||
LATTICE/莱迪斯 |
22+ |
DIP20 |
15 |
原装现货假一赔十 |
询价 | ||
N/A |
23+ |
DIP20 |
1778 |
专业优势供应 |
询价 | ||
LATTICE |
22+ |
PLCC |
2000 |
绝对进口原装现货 |
询价 | ||
Lattice Semiconductor Corporat |
21+ |
20PLCC |
13880 |
公司只售原装,支持实单 |
询价 | ||
LATTICE |
2021+ |
DIP |
6010 |
百分百原装正品 |
询价 | ||
LATTICE |
03+ |
DIP20 |
5 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
LATTICE |
18+ |
PLCC |
29477 |
全新原装现货,可出样品,可开增值税发票 |
询价 | ||
DIP |
46 |
询价 | |||||
LAT |
23+ |
589610 |
新到现货 原厂一手货源 价格秒杀代理! |
询价 |