High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

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All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

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High Performance E2CMOS PLD Generic Array Logic?

文件：654.14 Kbytes 页数：24 Pages

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High Performance E2CMOS PLD Generic Array Logic?

文件：395.51 Kbytes 页数：22 Pages

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High Performance E2CMOS PLD Generic Array Logic?

文件：339.82 Kbytes 页数：23 Pages

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High Performance E2CMOS PLD

文件：340.72 Kbytes 页数：23 Pages

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IC CPLD 8MC 25NS 20PLCC

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Package：20-LCC（J 形引线）；包装：管件 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 8MC 25NS 20PLCC

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