Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counte

文件：1.4977 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

Features ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compa

文件：1.49206 Mbytes 页数：65 Pages

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阿尔特

Programmable Logic Device Family

文件：1.49779 Mbytes 页数：66 Pages

ALTERA

阿尔特

Programmable Logic Device Family

General Description\nThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter

Intel

英特尔

Programmable Logic Device

General Description MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture. Features... ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

文件：1.01848 Mbytes 页数：64 Pages

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阿尔特