24-Bit Audio Digital Signal Processor

Overview This document briefly describes the DSP56367 24-bit digital signal processor (DSP). The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic e

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FREESCALEFreescale Semiconductor, Inc

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Implementing Viterbi Decoders Using the VSL Instruction on DSP Families

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MMACS at 3.0–3.6 V using an inter

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FREESCALEFreescale Semiconductor, Inc

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24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

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The DSP56371 is a high density CMOS device with 5.0-V compatible inputs and outputs

DSP56300 Core Description The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it. The DSP56300 core family offers a new le

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24-Bit Digital Signal Processor

Features High-Performance DSP56300 Core • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 ´ 24-bit parallel M

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DSP56307EVM Evaluation Module

FEATURES Hardware • 24-bit DSP56307 Digital Signal Processor – High -Performance DSP56300 core • 100 Million Instructions Per Second (MIPS) with a 100-MHz clock at 2.5-V core and 3.3 V I/O • Object code compatible with the DSP56000 core • Highly-parallel instruction set • Data Arithmetic L

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24-Bit Digital Signal Processor

DSP56321T Features High-Performance DSP56300 Core • 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C • Object code compatible with t

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24-Bit Digital Signal Processor

24-Bit Digital Signal ProcessorThe DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core\nincludes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309\noffers 100 MMACS at 3.0–3.6 V using an internal 100 MHz

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24-Bit Audio Digital Signal Processor

Overview The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56366 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined

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FREESCALEFreescale Semiconductor, Inc

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24-Bit Audio Digital Signal Processor

Features DSP56300 Modular Chassis • 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V. • Object Code Compatible with the 56K core. • Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. • Program Control with positi

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