24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

文件：2.28972 Mbytes 页数：124 Pages

FREESCALEFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP

24-Bit Digital Signal Processor

Features • 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V • Object code compatible with the DSP56000 core with highly parallel instruction set • Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier- Accumulator (MAC), 56

文件：2.83202 Mbytes 页数：124 Pages

恩XP