Features

• 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-

Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support

under software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), internal instruction cache

controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast

auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external

accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-ofblock-

transfer interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock

and output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

DSP56301属于集成电路（IC） > DSP（数字信号处理器）。恩智浦半导体公司制造生产的DSP56301DSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。