DSP56300中文资料恩XP数据手册PDF规格书

Features

High-Performance DSP56300 Core

• 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 ´ 24-bit parallel

Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under

software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,

on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;

one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer

interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and

output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCEÔ) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

On-Chip Coprocessors

• The Filter Coprocessor (FCOP) implements a wide variety of convolution and correlation filtering

algorithms. In GSM applications, the FCOP cross-correlates between the received training sequence

and a known midamble sequence to estimate the channel impulse response, and then performs match

filtering of received data symbols using coefficients derived from that estimated channel.

• The Viterbi Coprocessor (VCOP) implements a Maximum Likelihood Sequential Estimation (MLSE)

algorithm for channel decoding and equalization (uplink) and channel convolution coding (downlink).

The VCOP supports constraint lengths (k) of 4, 5, 6, or 7 with number of states 8, 16, 32, or 64,

respectively; code rates of 1/2, 1/3, 1/4, or 1/6; and trace-back Trellis depth of 36.

• The Cyclic-code Coprocessor (CCOP) executes cyclic code calculations for data ciphering and

deciphering, as well as parity code generation and check. The CCOP is fully programmable and not

dedicated to a specific algorithm, but it is well suited for GSM A5.1 and A5.2 data ciphering

algorithms. The CCOP can generate mask sequences for data ciphering, and supports Fire encode and

decode for burst error correction, as well as generation of Cyclic Redundancy Code (CRC) syndrome

for any polynomial of any degree up to 48.

On-Chip Peripherals

• 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to

other DSP563xx buses or ISA interface requiring only 74LS45-style buffers

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters

(allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which

peripherals are enabled