DSP56100中文资料摩托罗拉数据手册PDF规格书

The DSP56166 is the second member of Motorola’s DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in Σ∆ codec and phase locked loop (PLL). This MPU-style DSP also contains, memories, digital peripherals, and provides a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCE) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly simplified by using the OnCE. The DSP56166 RAM based is an off the shelf part since there are no user programmable ROM’s onchip. The DSP56166 ROM based contains a 12K ROM (8Kx 16 program ROM and 4Kx16 data ROM).

DSP56100 Family Features

• Up to 30 Million Instructions per Second (MIPS) at 60 MHz.– 33.3 ns Instruction cycle

• Single-cycle 16 x 16-bit parallel Multiply-Accumulate

• 2 x 40-bit accumulators with extension byte

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Highly parallel instruction set with unique DSP addressing modes

• Nested hardware DO loops including infinite loops and DO zero loop

• Two instruction LMS adaptive filter loop

• Fast auto-return interrupts

• Three external interrupt request pins

• Three 16-bit internal data and three 16-bit internal address buses

• Individual programmable wait states on the external bus for program, data, and peripheral memory spaces

• Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin

• On-chip memory-mapped peripheral registers

• Low Power Wait and Stop modes

• On-Chip Emulation (OnCE) for unobtrusive, processor speed independent debugging

• Operating frequency down to DC

• 5V single power supply

• Low power (HCMOS)