DS92LV1260 Six Channel 10 Bit BLVDS Deserializer

1FEATURES 2• Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rat

文件：777.84 Kbytes 页数：21 Pages

TI

德州仪器

Six Channel 10 Bit BLVDS Deserializer

文件：714.05 Kbytes 页数：21 Pages

TI

德州仪器

Six Channel 10 Bit BLVDS Deserializer

文件：366.66 Kbytes 页数：17 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

丝印：DS92LV1260TUJB；Package：NFBGA；DS92LV1260 Six Channel 10 Bit BLVDS Deserializer

1FEATURES 2• Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rat

文件：777.84 Kbytes 页数：21 Pages

TI

德州仪器

丝印：DS92LV1260TUJB；Package：NFBGA；DS92LV1260 Six Channel 10 Bit BLVDS Deserializer

1FEATURES 2• Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rat

文件：777.84 Kbytes 页数：21 Pages

TI

德州仪器

丝印：DS92LV1260TUJB；Package：NFBGA；DS92LV1260 Six Channel 10 Bit BLVDS Deserializer

1FEATURES 2• Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rat

文件：777.84 Kbytes 页数：21 Pages

TI

德州仪器

丝印：DS92LV1260TUJB；Package：NFBGA；DS92LV1260 Six Channel 10 Bit BLVDS Deserializer

1FEATURES 2• Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rat

文件：777.84 Kbytes 页数：21 Pages

TI

德州仪器

6 通道、10 位 B-LVDS Channel Link 解串器

The DS92LV1260 integrates six deserializer devices into a single chip. The chip uses a 0.25u CMOS process technology. The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments DS92LV1021 or DS92LV1023 Bus LVDS serializers. The device also • Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks\n• Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams\n• Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input\n• Parallel Clock Rate up to 40MHz\n• O;

TI

德州仪器

Six Channel 10 Bit BLVDS Deserializer

文件：714.05 Kbytes 页数：21 Pages

TI

德州仪器

Six Channel 10 Bit BLVDS Deserializer

文件：366.66 Kbytes 页数：17 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司