DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

文件：574.95 Kbytes 页数：20 Pages

TI

德州仪器

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：916.1 Kbytes 页数：17 Pages

MACOM

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：919.63 Kbytes 页数：17 Pages

TI

德州仪器

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：580.99 Kbytes 页数：12 Pages

NSC

国半

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

文件：165.48 Kbytes 页数：11 Pages

NSC

国半

3V BLVDS 1:6 时钟缓冲器/总线收发器

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high dat • Master/Slave Clock Selection in a Backplane Application \n• 125 MHz Operation (Typical)\n• 100 ps Duty Cycle Distortion (Typical)\n• 50 ps Channel to Channel Skew (Typical)\n• 3.3V Power Supply Design\n• Glitch-free Power on at CLKI/O Pins\n• Low Power Design (20 mA @ 3.3V Static)\n• Accepts Small;

TI

德州仪器

丝印：DS92CK16TMTC；Package：TSSOP；DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

文件：574.95 Kbytes 页数：20 Pages

TI

德州仪器

丝印：DS92CK16TMTC；Package：TSSOP；DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

文件：574.95 Kbytes 页数：20 Pages

TI

德州仪器

丝印：DS92CK16TMTC；Package：TSSOP；DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

文件：574.95 Kbytes 页数：20 Pages

TI

德州仪器

丝印：DS92CK16TMTC；Package：TSSOP；DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

1FEATURES 2• Master/Slave Clock Selection in a Backplane Application • 125 MHz Operation (Typical) • 100 ps Duty Cycle Distortion (Typical) • 50 ps Channel to Channel Skew (Typical) • 3.3V Power Supply Design • Glitch-free Power on at CLKI/O Pins • Low Power Design (20 mA @ 3.3V Static) •

文件：574.95 Kbytes 页数：20 Pages

TI

德州仪器