5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

文件：1.43382 Mbytes 页数：41 Pages

TI

德州仪器

5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

文件：960.55 Kbytes 页数：24 Pages

NSC

国半

5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

文件：1.08491 Mbytes 页数：30 Pages

NSC

国半

Spread Spectrum Tolerance Support Three key parameters, frequency

文件：162.35 Kbytes 页数：4 Pages

NSC

国半

5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 串行器

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional g • Supports Displays With 18-Bit Color Depth\n• 5-MHz to 43-MHz Pixel Clock\n• Automotive-Grade Product AEC-Q100 Grade 2 Qualified\n• 24:1 Interface Compression\n• Embedded Clock With DC Balancing Supports AC-Coupled Data Transmission\n• Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable\n•;

TI

德州仪器

Spread Spectrum Tolerance Support Three key parameters, frequency

文件：162.35 Kbytes 页数：4 Pages

NSC

国半

5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

文件：1.13118 Mbytes 页数：26 Pages

NSC

国半

5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

文件：960.55 Kbytes 页数：24 Pages

NSC

国半

5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

文件：1.43382 Mbytes 页数：41 Pages

TI

德州仪器

5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

文件：1.43382 Mbytes 页数：41 Pages

TI

德州仪器