DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

3V LVDS Quad CMOS Differential Line Receiver

文件：192.95 Kbytes 页数：9 Pages

NSC

国半

丝印：DS90LV032ATM；Package：SOIC；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032ATM；Package：SOIC；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032ATM；Package：SOIC；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032ATM；Package：SOIC；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032AT；Package：TSSOP；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032AT；Package：TSSOP；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032AT；Package：TSSOP；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器

丝印：DS90LV032AT；Package：TSSOP；DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver

1 Features 1• >400 Mbps (200 MHz) Switching Rates • 0.1-ns Channel-to-Channel Skew (Typical) • 0.1-ns Differential Skew (Typical) • 3.3-ns Maximum Propagation Delay • 3.3-V Power Supply Design • Power Down High Impedance on LVDS Inputs • Low Power Design (40 mW at 3.3 V Static) • Interoper

文件：667.06 Kbytes 页数：26 Pages

TI

德州仪器