DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

Dual Low Voltage Differential Signaling (LVDS) Receiver

文件：133.41 Kbytes 页数：8 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual Low Voltage Differential Signaling (LVDS) Receiver

文件：568.04 Kbytes 页数：8 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器

丝印：DS90C402M；Package：SOIC；DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

1FEATURES 2• Ultra Low Power Dissipation • Operates above 155.5 Mbps • Standard TIA/EIA-644 • 8 Lead SOIC Package saves PCB space • V CM ±1V center around 1.2V • ±100 mV Receiver Sensitivity DESCRIPTION The DS90C402 is a dual receiver device optimized for high data rate and low power ap

文件：518.429 Kbytes 页数：17 Pages

TI

德州仪器