DM9102F数据手册Davicom中文资料规格书

描述 Description

General Description
The DAVICOM’s DM9102 is a highly integrated single chip Fast Ethernet controller. It fully integrated 100BASE TX/10Base-T Fast Ethernet MAC, PHY and PMD. It is fully compliant with PCI Spec. 2.1 and IEEE802.3u.
The DM9102 provides a direct interface to the PCI local bus and direct connection to the network wire. As a controller, it provides the bus master capability. The DM9102 also supports auto-negotiation function that enables it to detect speed and duplex automatically. Due to the well-controlled rising/falling time, it requires no external filter to transmit signal to the media.

特性 Features

■ Single chip LAN controller integrated Fast Ethernet MAC, PHY and transceiver
■ Compliant with IEEE 802.3u 100BASE-TX, IEEE 802.3 10BASE-T and ANSI X3T12 TP-PMD standard
■ Direct interface to the PCI bus & fully compliant with PCI specification 2.1
■ PCI bus master architecture
■ Support PCI bus burst mode data transfer with programmable burst size
■ EEPROM 93C46 interface to store configuration information and user defined message
■ Support up to 256K bytes Boot ROM interface
■ Two large independent receive FIFO (4K) & transmit FIFO (2K) with programmable FIFO threshold and full packet burst processing
■ Support automatic packet deletion for runt packets and packet re-transmission with no FIFO reload
■ Support Full/Half Duplex operation
■ Physical, broadcast address recognition and 512-bit hash table algorithm for multicast address filtering
■ Compliant with IEEE802.3u Auto-negotiation protocol for automatic link type selection
■ High performance 100Mbps clock generator and data recovery circuit
■ Digital clock recovery circuit using advanced digital algorithm to reduce jitter
■ Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver
■ Provides Loopback mode for easy system diagnostics
■ 128 pin QFP with CMOS process