DM9102AE数据手册Davicom中文资料规格书

描述 Description

General Description
The DM9102A is a fully integrated and cost-effective single chip Fast Ethernet NIC controller. It is designed with low power and high performance process. It is a 3.3V device with 5V tolerance.

特性 Features

! Integrated Fast Ethernet MAC, Physical Layer and transceiver in one chip.
! 128pin QFP/128pin LQFP with CMOS process.
! +3.3V Power supply with +5V tolerant I/O.
! Complies with PCI specification 2.2.
! PCI clock up to 40MHz.
! PCI Bus master architecture.
! PCI Bus burst mode data transfer.
! Two large independent transmission and receipt of FIFO
! Up to 256K bytes Boot EPROM or Flash interface.
! EEPROM 93C46 interface automatically supports node ID load and configuration information.
! Complies with IEEE 802.3u 100Base-TX and 802.3 10Base-T.
! Complies with IEEE 802.3u auto-negotiation protocol for automatic link type selection.
! Supports IEEE 802.3x Full Duplex Flow Control
! VLAN frame length support.
! Complies with ACPI and PCI Bus Power Management.
! Supports the MII (Media Independent Interface) for an external PHY
! Supports Wake-On-LAN function and remote wake-up (Magic packet, Link Change and Microsoft® wake-up frame).
! Supports 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, active high, active low.)
! High performance 100Mbps clock generator and data recovery circuit.
! Digital clock recovery circuit, using advanced digital algorithm to reduce jitter.
! Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver.
! Provides Loopback mode for easy system diagnostics.
! Low power consumption modes:
  - Power reduced mode (cable detection)
\u0001  - Power down mode
\u0001  - Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction.