DM9102AT数据手册Davicom中文资料规格书

描述 Description

General Description
The DM9102A is a fully integrated and cost-effective single chip Fast Ethernet NIC controller. It is designed with the low power and high performance process. It is a 3.3V device with 5V tolerance then it supports 3.3Vand 5V signaling.
The DM9102A provides direct interface to the PCI or the CardBus. It supports bus master capability and fully complies with PCI 2.2. In media side, The DM9102A interfaces to the UTP3,4,5 in 10Base-T and UTP5 in 100Base-TX. It is fully compliance with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9102A to take the maximum advantage of its abilities. The DM9102A is also support IEEE 802.3x full duplex flow control.
The DM9102A supports two types of power-management mechanisms. The main mechanism is based upon the OnNow architecture, which is required for PC99. The alternative mechanism is based upon theremote Wake-On LAN mechanism.

特性 Features

■ Integrated Fast Ethernet MAC, Physical Layer and transceiver in one chip.
■ 128pin QFP/128pin TQFP with CMOS process.
■ +3.3V Power supply with +5V tolerant I/O.
■ Supports PCI and CardBus interfaces.
■ Comply with PCI specification 2.2.
■ PCI clock up to 40MHz.
■ PCI bus master architecture.
■ PCI bus burst mode data transfer.
■ Two large independent FIFO; receive FIFO & transmit FIFO.
■ Up to 256K bytes Boot EPROM or Flash interface.
■ EEPROM 93C46 interface supports node ID accesses configuration information and user define message.
■ Node address auto-load and reload.
■ Comply with IEEE 802.3u 100Base-TX and 802.3 10Base-T.
■ Comply with IEEE 802.3u auto-negotiation protocol for automatic link type selection.
■ Full Duplex/Half Duplex capability.
■ Support IEEE 802.3x Full Duplex Flow Control
■ VLAN support.
■ Comply with ACPI and PCI Bus Power Management.
■ Supports the MII (Media Independent Interface).
■ Supports Wake-On-LAN function and remote wake-up (Magic packet, Link Change and Microsoft® wake-up frame).
■ Supports 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, active high , active low ).
■ High performance 100Mbps clock generator and data recovery circuit.
■ Digital clock recovery circuit using advanced digital algorithm to reduce jitter.
■ Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver.
■ Provides Loopback mode for easy system diagnostics.