8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

Kingston DDR4 DRAM for embedded applications

Kingston on-board DDR4 DRAM is designed to meet the needs of embedded applications and offers a high speed option with lower power consumption. KEY FEATURES • Double-data-rate architecture: two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch p

文件：4.1171 Mbytes 页数：2 Pages

KINGSTON

金士顿

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

Kingston DDR4 DRAM for embedded applications

Kingston on-board DDR4 DRAM is designed to meet the needs of embedded applications and offers a high speed option with lower power consumption. KEY FEATURES • Double-data-rate architecture: two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch p

文件：4.1171 Mbytes 页数：2 Pages

KINGSTON

金士顿

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

8G bits DDR4 SDRAM

• Features • Double-data-rate architecture: two data transfers per clock cycle. • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：1.6526 Mbytes 页数：41 Pages

KINGSTON

金士顿

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate (DDR) architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 页数：2 Pages

KINGSTON

金士顿

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES • Double Data Rate architecture: two data transfers per clock cycle • High-speed data transfer is realized by 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver • DOS

文件：425.79 Kbytes 页数：2 Pages

KINGSTON

金士顿