4G bist DDR3L SDRAM

Features * Doubledatarate archiectne Wo datatranslers perclodk oyoe * Thehghspesd data tanster isiealzed by he 8 bts preletch ppeined achiectue * BKdectonal diflerontal data stobe (0QS and /DQ8) s tanemitedheceted WMh data for captuing data 不 the receiver * DQSisedgeaigned wih dataforREADs

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KINGSTON

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DDR3/3L DRAM for embedded applications

• Double-data-rate architecture: two data transfers per clock cycle\r\n• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture\r\n• Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver\r\n• DOS is;

Kingston

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DRAM Components

Kingston

金士顿

英飞凌

上传：深圳市铭威达电子科技有限公司

FCBGA559

Intel

英特尔

上传：深圳市英科美电子有限公司