Configurable UART with FIFO ver 2.08

OVERVIEW The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data p

文件：186.04 Kbytes 页数：7 Pages

DCD

Digital Core Design

Configurable UART with FIFO ver 2.08

DCD

High Performance Configurable 8-bit RISC Microcontroller

文件：187.11 Kbytes 页数：7 Pages

DCD

Digital Core Design

High Performance Configurable 8-bit RISC Microcontroller

OVERVIEW The DRPIC1655X is a low-cost, high per ormance, 8-bit, fully static soft IP Core, dedicated for operation with fast (typically onchip) dual ported memory. The core has been designed with a special concern about low power consumption. DRPIC1655X soft core is softwarecompatible with the i

文件：197.97 Kbytes 页数：8 Pages

DCD

Digital Core Design

3A DDR Bus Termination Regulator

Description The FAN1655 is a low-cost bi-directional LDO specifically designed for terminating DDR memory bus. It can both sink and source up to 2.1A continuous, 3A peak, providing enough current for most DDR applications. Load regulation meets the JEDEC spec, VTT = VREFOUT ± 40mV. The FAN1655 i

文件：513.539 Kbytes 页数：9 Pages

FAIRCHILD

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