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D16550中文资料DCD数据手册PDF规格书

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厂商型号

D16550

功能描述

Configurable UART with FIFO ver 2.08

文件大小

186.04 Kbytes

页面数量

7

生产厂商

DCD Digital Core Design

网址

网址

数据手册

下载地址一下载地址二

更新时间

2026-3-9 22:55:00

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D16550规格书详情

OVERVIEW

The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-toparallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.

KEY FEATURES

● Software compatible with 16450 and 16550 UARTs

● Configuration capability

● Separate configurable BAUD clock line

● Two modes of operation: UART mode and FIFO mode

● Majority Voting Logic

● In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU

● Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data

● In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data

● Independently controlled transmit, receive, line status, and data set interrupts

● False start bit detection

● 16 bit programmable baud generator

● MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)

○ Fully programmable serial-interface characteristics:

○ 5-, 6-, 7-, or 8-bit characters

○ Even, odd, or no-parity bit generation and

○ 1-, 1½-, or 2-stop bit generation detection

○ Baud generation

● Complete status reporting capabilities

● Line break generation and detection. Internal diagnostic capabilities:

○ Loop-back controls for communications link fault isolation

○ Break, parity, overrun, framing error simulation

● Two DMA Modes allows single and multitransfer

● Technology independent HDL Source Code

● Full prioritized interrupt system controls

● Fully synthesizable static design with no internal tri-state buffers

APPLICATIONS

● Serial Data communications applications

● Modem interface

产品属性

  • 型号:

    D16550

  • 制造商:

    DCD

  • 制造商全称:

    DCD

  • 功能描述:

    Configurable UART with FIFO ver 2.08

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