144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Features ■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 450-MHz clock for high ban

文件：783.79 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Functional Description The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Features ■ 144-Mbit density (8 M × 18, 4 M × 36) ■ 450-MHz clock for high ban

文件：783.79 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

16K x 4 Static RAM

文件：266.19 Kbytes 页数：9 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

16K x 4 Static RAM

文件：266.19 Kbytes 页数：9 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

16K x 4 Static RAM

文件：266.19 Kbytes 页数：9 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

文件：861.72 Kbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

文件：861.72 Kbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

文件：861.72 Kbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

文件：861.72 Kbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

文件：861.72 Kbytes 页数：31 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司