36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Functional Description The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33[1] are 3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version)

文件：572.31 Kbytes 页数：31 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e

文件：392.04 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e

文件：392.04 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e

文件：392.04 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-e

文件：392.04 Kbytes 页数：27 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司