18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18 Mbit (512 K 횞 36/1 M 횞 18) Flow Through SRAM

文件：1.15175 Mbytes 页数：34 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

文件：1.10335 Mbytes 页数：37 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

文件：1.22244 Mbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Functional Description [1] The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip

文件：469.2 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司