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CY7C1340F

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-100AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-100AI

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-133AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-133AI

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-166AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-166AI

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-200AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-200AI

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

CY7C1340F-225AC

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件:348.94 Kbytes 页数:17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

详细参数

  • 型号:

    CY7C1340F

  • 制造商:

    Cypress Semiconductor

  • 功能描述:

    SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 4.5ns 100-Pin TQFP

  • 制造商:

    Rochester Electronics LLC

  • 功能描述:

    128KX32 3.3V SYNC-PL 2CD SRAM(3.3V I/O) - Bulk

供应商型号品牌批号封装库存备注价格
Cypress
16+
原厂封装
10000
全新原装正品,代理优势渠道供应,欢迎来电咨询
询价
24+
N/A
82000
一级代理-主营优势-实惠价格-不悔选择
询价
CYPRESS/赛普拉斯
2450+
TQFP
6540
只做原厂原装正品现货或订货!终端工厂可以申请样品!
询价
CYP
23+
贴片
5000
原装正品,假一罚十
询价
CYP
24+
N/A
5650
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
CYP
25+
72
4500
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
cypress
2138+
原厂标准封装
8960
代理CYPRESS全系列芯片,原装现货
询价
CYP
23+
原厂正规渠道
5000
专注配单,只做原装进口现货
询价
CY
24+
原厂封装
65250
支持样品,原装现货,提供技术支持!
询价
cypress
25+
10
公司优势库存 热卖中!
询价
更多CY7C1340F供应商 更新时间2026-2-2 10:11:00