4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件：348.94 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件：348.94 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •

文件：348.94 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mb (128K x 32) Pipelined DCD Sync SRAM

Infineon

英飞凌