128K x 36 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All

文件：730.18 Kbytes 页数：17 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 36 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All

文件：730.18 Kbytes 页数：17 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 36 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All

文件：730.18 Kbytes 页数：17 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

128K x 36 Synchronous-Pipelined Cache RAM

Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All

文件：730.18 Kbytes 页数：17 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司