4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

文件：340.45 Kbytes 页数：17 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司