4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

文件：373.23 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Pipelined Sync SRAM

Features • Registered inputs and outputs for pipelined operation • 256K ×18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.6 ns (for 225-MHz device) — 2.8 ns (for 200-MHz device) — 3.5

文件：340.8 Kbytes 页数：18 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司