4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write

文件：805.37 Kbytes 页数：21 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

文件：337.24 Kbytes 页数：16 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司