18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：327.27 Kbytes 页数：22 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb QDR™-II SRAM 4-Word Burst Architecture

Functional Description\nThe CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write • Separate Independent Read and Write Data Ports\n   — Supports concurrent transactions\n• 250-MHz Clock for High Bandwidth\n• 4-Word Burst for reducing address bus frequency\n• Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz\n• Two input clock;

Infineon

英飞凌

18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：327.27 Kbytes 页数：22 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：327.27 Kbytes 页数：22 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri

文件：327.27 Kbytes 页数：22 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司