3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

文件：264.97 Kbytes 页数：10 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

文件：382.01 Kbytes 页数：10 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Infineon

英飞凌

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

文件：166.08 Kbytes 页数：8 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司