CDCLVP1204

低抖动 2 路输入可选 1:4 通用至 LVPECL 缓冲器; • 2:4 Differential Buffer\n• Selectable Clock Inputs Through Control Terminal\n• Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL\n• Four LVPECL Outputs\n• Maximum Clock Frequency: 2 GHz\n• Maximum Core Current Consumption: 45 mA\n• Very Low Additive Jitter: to 20-MHz Offset Range: \n• 57 fs, RMS (typical) at 122.88 MHz\n• 48 fs, RMS (typical) at 156.25 MHz\n• 30 fs, RMS (typical) at 312.5 MHz\n \n• 2.375-V to 3.6-V Device Power Supply\n• Maximum Propagation Delay: 450 ps\n• Maximum Output Skew: 15 ps\n• LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs\n• Industrial Temperature Range: –40°C to +85°C\n• Supports 105°C PCB Temperature (Measured at Thermal Pad)\n• ESD Protection Exceeds 2 kV (HBM);

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1204 is characterized for operation from –40°C to +85°C.

CDCLVP1208

低抖动 2 路输入可选 1:8 通用至 LVPECL 缓冲器; • 2:8 Differential Buffer\n• Selectable Clock Inputs Through Control terminal\n• Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL\n• Eight LVPECL Outputs\n• Maximum Clock Frequency: 2 GHz\n• Maximum Core Current Consumption: 73 mA\n• Very Low Additive Jitter: 20 MHz Offset Range: \n• 57 fs, rms (typical) at 122.88 MHz\n• 48 fs, rms (typical) at 156.25 MHz\n• 30 fs, rms (typical) at 312.5 MHz\n \n• 2.375-V to 3.6-V Device Power Supply\n• Maximum Propagation Delay: 450 ps\n• Maximum Output Skew: 20 ps\n• LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs\n• Industrial Temperature Range: –40°C to 85°C \n• Supports 105°C PCB Temperature (Measured with a Thermal Pad)\n• ESD Protection Exceeds 2 kV (HBM)\n• Available in 5-mm × 5-mm QFN-28 (RHD) Package;

The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1208 is packaged in a small 28-pin,5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.

CDCLVP1204

Two LVPECL Output, High-Performance Clock Buffer

CDCLVP1204_15

Four LVPECL Output, High-Performance Clock Buffer

CDCLVP1204RGTR

Four LVPECL Output, High-Performance Clock Buffer

CDCLVP1204RGTR

Four LVPECL Output, High-Performance Clock Buffer

CDCLVP1204RGTT

Four LVPECL Output, High-Performance Clock Buffer

CDCLVP1204RGTT

Four LVPECL Output, High-Performance Clock Buffer

CDCLVP1208

Eight LVPECL Output, High-Performance Clock 2:8 Buffer

CDCLVP1208RHDR

Eight LVPECL Output, High-Performance Clock 2:8 Buffer