CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：863.58 Kbytes 页数：30 Pages

TI

德州仪器

CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：904.4 Kbytes 页数：33 Pages

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德州仪器

Two LVPECL Output, High-Performance Clock Buffer

文件：753.48 Kbytes 页数：22 Pages

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德州仪器

低抖动 2 路输入可选 1:4 通用至 LVPECL 缓冲器

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-ch • 2:4 Differential Buffer\n• Selectable Clock Inputs Through Control Terminal\n• Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL\n• Four LVPECL Outputs\n• Maximum Clock Frequency: 2 GHz\n• Maximum Core Current Consumption: 45 mA\n• Very Low Additive Jitter: to 20-MHz Offset Range: \n• 57 fs, ;

TI

德州仪器

CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：904.4 Kbytes 页数：33 Pages

TI

德州仪器

丝印：1204；Package：VQFN(RGT)；CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：904.4 Kbytes 页数：33 Pages

TI

德州仪器

丝印：1204；Package：VQFN；CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：863.58 Kbytes 页数：30 Pages

TI

德州仪器

丝印：1204；Package：VQFN(RGT)；CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：904.4 Kbytes 页数：33 Pages

TI

德州仪器

丝印：1204；Package：VQFN；CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：863.58 Kbytes 页数：30 Pages

TI

德州仪器

丝印：1204；Package：VQFN(RGT)；CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer

1 Features 1• 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter:

文件：904.4 Kbytes 页数：33 Pages

TI

德州仪器