CDCE949中文资料具有 2.5V 或 3.3V LVCMOS 输出的可编程 4-PLL VCXO 时钟合成器数据手册TI规格书

描述 Description

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949. The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.The deep M/N divider ratio allows the generation of zero-ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI). Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration. It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.

特性 Features

• Member of Programmable Clock Generator Family
• CDCEx913: 1 PLLs, 3 Outputs
• CDCEx925: 2 PLLs, 5 Outputs
• CDCEx937: 3 PLLs, 7 Outputs
• CDCEx949: 4 PLLs, 9 Outputs

• In-System Programmability and EEPROM
• Serial Programmable Volatile Register
• Nonvolatile EEPROM to Store Customer Settings

• Flexible Input Clocking Concept
• External Crystal: 8 to 32 MHz
• On-Chip VCXO: Pull-Range ±150 ppm
• Single-Ended LVCMOS Up to 160 MHz

• Free Selectable Output Frequency Up to 230 MHz
• Low-Noise PLL Core
• PLL Loop Filter Components Integrated
• Low Period Jitter (Typical 60 ps)

• Separate Output Supply Pins
• CDCE949: 3.3 V and 2.5 V
• CDCEL949: 1.8 V

• Flexible Clock Driver
• Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable or Power Down
• Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
• Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
• Programmable SSC Modulation
• Enables 0-PPM Clock Generation

• 1.8-V Device Core Supply
• Wide Temperature Range: –40°C to 85°C
• Packaged in TSSOP
• Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)

简介

CDCE949属于集成电路（IC）的时钟发生器PLL频率合成器。由TI制造生产的CDCE949时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。