CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 页数：31 Pages

TI

德州仪器

用于 PCIe® 第 1 代至第 5 代的 8 输出时钟缓冲器，具有可选的 SMBus 地址

CDCDB803 是一款符合 DB800ZL 标准的 8 路输出 LP-HCSL 时钟缓冲器，能够为第 1 代到第 5 代 PCIe、QuickPath Interconnect (QPI)、UPI、SAS 和 SATA 接口分配基准时钟。使用 SMBus 接口和 8 输出使能引脚，可以单独配置和控制所有 8 个输出。 CDCDB803 是一款 DB800ZL 衍生缓冲器，符合或超过 DB800ZL 中的系统参数规格。它还符合或超过了 DB2000Q 的参数规格。 CDCDB803 采用 6mm × 6mm 48 引脚 VQFN 封装。 • 具有可编程集成 85Ω（默认值）或 100Ω 差分输出终端的 8 个 LP-HCSL 输出\n• 使用第 5 代 PCIE 滤波器之后的附加相位抖动： \n• 可编程输出转换率控制 \n• 3.3V 内核和 IO 电源电压\n• 电流消耗：72mA（最大值）\n• 6mm × 6mm 48 引脚 VQFN 封装;

TI

德州仪器

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 页数：31 Pages

TI

德州仪器

丝印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 页数：31 Pages

TI

德州仪器