型号：CDCDB803ERSLR；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI1

德州仪器

型号：CDCDB803ERSLT；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI1

德州仪器

型号：CDCDB803RSLR；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI1

德州仪器

型号：CDCDB803RSLT；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 页数：34 Pages

TI1

德州仪器

型号：CDCDB803RSLR；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 页数：31 Pages

TI

德州仪器

型号：CDCDB803RSLT；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 页数：31 Pages

TI

德州仪器