CDCDB803集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

CDCDB803属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的CDCDB803时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

• 8 LP-HCSL outputs with programmable integrated

85-Ω (default) or 100-Ω differential output

terminations

• 8 hardware output enable (OE#) controls

• Additive phase jitter after PCIE Gen 6 filter: 20 fs,

RMS (maximum)

• Additive phase jitter after PCIE Gen 5 filter: 25 fs,

RMS (maximum)

• Additive phase jitter after DB2000Q filter: 38 fs,

RMS (maximum)

• Supports Common Clock (CC) and Individual

Reference (IR) architectures

– Spread spectrum-compatible

• Output-to-output skew: < 50 ps

• Input-to-output delay: < 3 ns

• Fail-safe input

• Programmable output slew rate control

• 9 selectable SMBus addresses

• 3.3-V core and IO supply voltages

• Hardware-controlled low power mode (PD#)

• Current consumption: 72 mA maximum

• 6-mm × 6-mm, 48-pin VQFN package

2 Applications

• Microserver & tower server

• Storage area network & host bus adapter card

• Network attached storage

• Hardware accelerator

• Rack server

3 Description

The CDCDB803 is a 8-output LP-HCSL, DB800ZLcompliant,

clock buffer capable of distributing the

reference clock for PCIe Gen 1-6, QuickPath

Interconnect (QPI), UPI, SAS, and SATA interfaces.

The SMBus interface and eight output enable pins

allow the configuration and control of all eight

outputs individually. The CDCDB803 is a DB800ZL

derivative buffer and meets or exceeds the system

parameters in the DB800ZL specification. It also

meets or exceeds the parameters in the DB2000Q

specification. The CDCDB803 is packaged in a 6-mm

× 6-mm, 48-pin VQFN package.